1. Field of the Invention
The invention relates to display apparatus driving circuitry, and in particular relates to display apparatus driving circuitry for driving a plasma display panel.
2. Prior Art
In recent years, plasma display panels (hereinafter referred to as ‘PDPs’), which can be made large in size and can be made thin and light-weight, have come into the limelight as display apparatuses in television broadcast receivers, personal computers and so on. FIG. 9 shows schematically an example of the constitution of a PDP driving apparatus for driving a PDP.
For the sake of simplicity, the case of a two-electrode PDP 100 is shown in FIG. 9. The driving apparatus for the PDP 100 is constituted from a plurality of scan driver ICs (Integrated Circuits) 101-1, 101-2, 101-3, . . . , 101-n and data (address) driver ICs 102-1, 102-2, 102-3, . . . , 102-m and so on (here, n and m are arbitrary integers).
The scan driver ICs 101-1 to 101-n each drive a plurality of scanning/sustaining electrodes 111, and the data (address) driver ICs 102-1 to 102-m each drive a plurality of data electrodes 112 corresponding to the colors red, green and blue. These scanning/sustaining electrodes 111 and data electrodes 112 are arranged in a grid so as to be perpendicular to one another, and electrical discharge cells (not shown) are disposed at the points of intersection therebetween.
If, for example, each of the scan driver ICs 101-1 to 101-n can drive 64 scanning/sustaining electrodes 111, then in the case that the pixels of the PDP 100 form an XGA (extended video Graphics Array), the number of pixels will be 1024×768, and hence the number of scan driver ICs 101-1 to 101-n will be 12.
When displaying an image, using the scan driver ICs 101-1 to 101-n and data (address) driver ICs 102-1 to 102-m, data from the data electrodes 112 is written into the electrical discharge cells while scanning through the scanning/sustaining electrodes 111 one at a time, and electrical discharge sustaining pulses are outputted to the scanning/sustaining electrodes 111 to sustain the electrical discharges for an electrical discharge sustaining period, whereby display of the image is carried out.
Here, for the case of a conventional scan driver IC (hereinafter referred to as ‘display apparatus driving circuitry’), a description will be given of the output stage circuitry for the part driving one scan line, with reference to FIG. 10. FIG. 10 is a circuit diagram of the output stage in conventional PDP display apparatus driving circuitry. The circuitry of FIG. 10 has a level shifter circuit 121, a buffer circuit 130, and two IGBTs (Insulated Gate Bipolar Transistors) 122 and 123, which are devices through which a large current can be passed per unit area.
The level shifter circuit 121 is constituted from a high-voltage-resistant PMOS or NMOS, not shown. Moreover, an input terminal 141 into which a signal (0 to 5 volts) is inputted from a control circuit, not shown, is connected to the level shifter circuit 121. The level shifter circuit 121 converts this signal into a signal of 0 to 100 volts, and inputs the converted signal into the gate of the IGBT 122.
The buffer circuit 130 is connected to an input terminal 142. A 0 to 5 volt signal is inputted to the input terminal 142 from a control circuit, not shown. The output from the buffer circuit 130 is outputted into the gate of the IGBT 123.
The conventional buffer circuit 130 is constituted from a CMOS (Complementary MOS). It includes a p-channel type MOSFET (Metal Oxide Semiconductor Field Effect Transistor (hereinafter merely referred to as a ‘PMOS’) 131 and an n-channel type MOSFET (hereinafter merely referred to as an ‘NMOS’) 132. The gates of the PMOS 131 and the NMOS 132 are both connected to the input terminal 142. The source of the PMOS 131 is connected to a low-voltage power supply terminal VDL. A low voltage of 0 to 5 volts for logic is supplied from the low-voltage power supply terminal VDL. The drain of the PMOS 131 is connected to the gate of the IGBT 123 and the drain of the NMOS 132. The source of the NMOS 132 is connected (grounded) to a reference power supply terminal GND (hereinafter merely referred to as ‘GND’).
The collector terminal of the IGBT 122 is connected to a high-voltage power supply terminal VDH from which a high voltage of 0 to 100 volts is supplied. The emitter of the IGBT 122 is connected to an output terminal OUT and the collector of the IGBT 123. Moreover, the emitter of the IGBT 123 is connected to GND.
The output terminal OUT is connected to a scanning/sustaining electrode 111 as shown in FIG. 9. It is further connected to an electrical discharge cell (which can be regarded as a capacitor C).
Note that in the following, a voltage of 100 volts supplied from the high-voltage power supply terminal VDH is sometimes referred to merely as ‘VDH’, and a voltage of 5 volts supplied from the low-voltage power supply terminal VDL is sometimes referred to merely as ‘VDL’.
With such circuitry, for example, when a signal of 0 to 5 volts is inputted to the input terminal 141, and hence the input terminal 141 becomes ‘H’, this signal is converted into a signal of 0 to 100 volts by the level shifter circuit 121, and hence the gate of the IGBT 122 is made to be ‘H’, and thus the IGBT 122 is turned on, and hence a signal with a high voltage of 100 volts is outputted to the output terminal OUT.
At the time of an address electrical discharge (writing using a data electrode 112 as described earlier), it is necessary to turn the IGBT 123 on, and thus reduce the potential at the output terminal OUT to 0 volts. To do this, the input terminal 141 is made to be ‘L’, and the signal of 0 to 5 volts at the input terminal 142 is made to be ‘L’, whereby, through the CMOS buffer circuit 130, the gate of the IGBT 123 is made to be ‘H’ (VDL) and hence the IGBT 123 is turned on. As a result 0 volts, i.e. the same potential as at the reference power supply terminal GND, is outputted to the output terminal OUT.
Here, part of the voltage and current waveforms during an address electrical discharge are shown for the output stage circuitry of the conventional display apparatus driving circuitry for driving a PDP shown in FIG. 10.
FIG. 11 is a timing diagram showing part of the voltage and current waveforms during an address electrical discharge for the output stage circuitry of the conventional display apparatus driving circuitry for driving a PDP.
Here, the relationship between the potential Vo at the output terminal OUT and the current Ic flowing into the collector of the IGBT 123 will be shown.
At time t1, the IGBT 123 is turned on, whereupon the potential Vo starts to drop to 0 V; at this time, a current IP flows into the GND connected to the emitter of the IGBT 123 due to charge stored in the electrical discharge cell connected to the output terminal OUT. When the potential Vo reaches 0 at time t2, the current IP stops flowing, and then once the effective voltage due to a high voltage applied to the data electrode 112 (see FIG. 9) has become sufficiently high (time t3), a plasma discharge is started, and hence a discharge current IH flows. The discharge current IH stops flowing at a time t4.
As the output stage circuitry in such display apparatus driving circuitry for driving a PDP, there is also circuitry in which, for example, the number of components in the circuitry is reduced by using a horizontal thyristor of an insulated gate type having no channel formed therein (see, for example, Japanese Patent Application Laid-open No. 2002-176168 (paragraphs nos. 0021 to 0026 and FIG. 3)
However, with conventional display apparatus driving circuitry, in the case in particular that devices having a large current driving capacity such as IGBTs are used so that a large current can be passed during an address electrical discharge, there has been a problem that the driving capacity is too great. This causes the waveform of the output potential to drop sharply (between times t1 to t2 in FIG. 11), and thus noise is prone to occur.
Moreover, there has been a problem that an excessive current tends to flow upon short-circuiting of the output terminal. This makes the circuit prone to damage.